Invention Grant
- Patent Title: Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
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Application No.: US14251258Application Date: 2014-04-11
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Publication No.: US09613847B2Publication Date: 2017-04-04
- Inventor: Mark A. Bachman , Sailesh M. Merchant , John Osenbach
- Applicant: LSI Corporation
- Applicant Address: SG Singapore
- Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Sheridan Ross P.C.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/768 ; H01L23/48
Abstract:
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.
Public/Granted literature
- US20140220760A1 INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS Public/Granted day:2014-08-07
Information query
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