Invention Grant
- Patent Title: Method and apparatus for back end of line semiconductor device processing
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Application No.: US14853104Application Date: 2015-09-14
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Publication No.: US09613854B2Publication Date: 2017-04-04
- Inventor: Shin-Yi Yang , Hsiang-Huan Lee , Ming-Han Lee , Ching-Fu Yeh , Pei-Yin Liou
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.
Public/Granted literature
- US20160005648A1 Method and Apparatus for Back End of Line Semiconductor Device Processing Public/Granted day:2016-01-07
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