Invention Grant
- Patent Title: Semiconductor die and die cutting method
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Application No.: US14990830Application Date: 2016-01-08
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Publication No.: US09613865B2Publication Date: 2017-04-04
- Inventor: Jyishyang Liu , Xuanjie Liu , Xiaojun Chen , Lushan Jiang
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicant Address: CN Shanghai
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Anova Law Group, PLLC
- Priority: CN201510011960 20150109
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/66

Abstract:
The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A device layer, an interconnection layer, and a soldering pad layer are formed on the semiconductor substrate. The soldering layer includes a plurality of soldering pads. A passivation layer covers the soldering pads and the interconnect layer, and is etched to form trenches on the soldering pads above the core regions and the test region. The passivation layer, the interconnect layer, and the device layer are etched to form isolation trenches at junctions of the isolation region and the test region, disconnecting the passivation layer, the interconnect layer and the device layer. A cutting process is performed along the test region, each of the semiconductor substrate, the device layer, the interconnect layer and the soldering pad layer is cut in two.
Public/Granted literature
- US20160204071A1 SEMICONDUCTOR DIE AND DIE CUTTING METHOD Public/Granted day:2016-07-14
Information query
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