- Patent Title: Method and system for manufacturing semiconductor epitaxy structure
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Application No.: US15194107Application Date: 2016-06-27
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Publication No.: US09613875B2Publication Date: 2017-04-04
- Inventor: Takashi Kobayashi , Po-Jung Lin , Che-Lin Chen , Bu-Chin Chung
- Applicant: HERMES-EPITEK CORP.
- Applicant Address: TW Taipei
- Assignee: HERMES-EPITEK CORP.
- Current Assignee: HERMES-EPITEK CORP.
- Current Assignee Address: TW Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/67 ; H01L21/02 ; H01L21/66 ; C23C16/22
Abstract:
A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition apparatus is configured for sequentially depositing a buffer layer, a first epitaxy layer, an insertion layer, a second epitaxy layer on a substrate. The curvature monitor system is configured for monitoring a curvature value of the semiconductor epitaxy structure. The control unit is configured for controlling the deposition apparatus to stop depositing the buffer layer, the first epitaxy layer, the insertion layer and the second epitaxy layer according to the curvature value of the semiconductor epitaxy structure measured by the curvature monitor system. The above-mentioned system for manufacturing semiconductor epitaxy structure is able to effectively control the strain of the semiconductor epitaxy structure during growth. A method for manufacturing semiconductor epitaxy structure is also disclosed.
Public/Granted literature
- US20160379904A1 METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR EPITAXY STRUCTURE Public/Granted day:2016-12-29
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