Invention Grant
- Patent Title: Ultralow power carbon nanotube logic circuits and method of making same
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Application No.: US14511705Application Date: 2014-10-10
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Publication No.: US09613879B2Publication Date: 2017-04-04
- Inventor: Mark C. Hersam , Michael L. Geier , Pradyumna L. Prabhumirashi , Weichao Xu , Hyungil Kim
- Applicant: NORTHWESTERN UNIVERSITY , REGENTS OF THE UNIVERSITY OF MINNESOTA
- Applicant Address: US IL Evanston US MN Minneapolis
- Assignee: NORTHWESTERN UNIVERSITY,REGENTS OF THE UNIVERITY OF MINNESOTA
- Current Assignee: NORTHWESTERN UNIVERSITY,REGENTS OF THE UNIVERITY OF MINNESOTA
- Current Assignee Address: US IL Evanston US MN Minneapolis
- Agency: Locke Lord LLP
- Agent Tim Tingkang Xia, Esq.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L23/31 ; H03K19/0948 ; H01L51/00 ; H01L51/05
Abstract:
In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.
Public/Granted literature
- US20150102288A1 ULTRALOW POWER CARBON NANOTUBE LOGIC CIRCUITS AND METHOD OF MAKING SAME Public/Granted day:2015-04-16
Information query
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