Invention Grant
- Patent Title: Low resistivity damascene interconnect
-
Application No.: US14809266Application Date: 2015-07-26
-
Publication No.: US09613907B2Publication Date: 2017-04-04
- Inventor: Ganesh Hegde , Mark S. Rodder , Jorge A. Kittl , Robert C. Bowen
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768

Abstract:
A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.
Public/Granted literature
- US20160035675A1 LOW RESISTIVITY DAMASCENE INTERCONNECT Public/Granted day:2016-02-04
Information query
IPC分类: