The present disclosure relates to methods of forming a field effect transistor (FET) over a substrate, and associated integrated circuit device that improve etching back profile and prevent metal gate defect. In some embodiments, a recess is formed through an inter-layer dielectric (ILD) layer along a sidewall spacer and filled with a high-κ dielectric layer and a metal gate. An etch back is performed to lower the high-κ dielectric layer and the metal gate, where an “antenna” shaped residue of the high-κ dielectric material and the metal gate material is left at the boundary region of the high-κ layer and the metal gate, along the sidewall spacer. Then a second etch is performed to the sidewall spacer, removing a top edge portion of the sidewall spacer. Then one more step of etch can be performed to the high-κ layer and the metal gate to planarize and remove the residue.