Invention Grant
- Patent Title: Semiconductor device including a memory cell
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Application No.: US13034278Application Date: 2011-02-24
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Publication No.: US09613964B2Publication Date: 2017-04-04
- Inventor: Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
- Applicant: Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2010-041852 20100226
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L27/105 ; G11C11/24 ; H01L27/1156 ; H01L27/12 ; H01L49/02

Abstract:
A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.
Public/Granted literature
- US20110210339A1 SEMICONDUCTOR DEVICE Public/Granted day:2011-09-01
Information query
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