Invention Grant
- Patent Title: Select gates with central open areas
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Application No.: US14808475Application Date: 2015-07-24
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Publication No.: US09613971B2Publication Date: 2017-04-04
- Inventor: Masahiro Yaegashi , Kota Funayama , Takeshi Kawamura , Dai Iwata
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: Foley & Lardner LLP
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L27/11524 ; H01L29/49 ; H01L29/40 ; H01L21/265 ; H01L21/28 ; H01L29/788 ; H01L29/167 ; H01L21/768 ; H01L21/02 ; H01L23/528
Abstract:
A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.
Public/Granted literature
- US20170025425A1 Select Gates with Central Open Areas Public/Granted day:2017-01-26
Information query
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