Invention Grant
- Patent Title: Bridge line structure for bit line connection in a three-dimensional semiconductor device
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Application No.: US14675162Application Date: 2015-03-31
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Publication No.: US09613975B2Publication Date: 2017-04-04
- Inventor: Chenche Huang , Chun-Ming Wang , Yuki Mizutani , Hiroaki Koketsu , Masayuki Hiroi , Masaaki Higashitani
- Applicant: SANDISK TECHNOLOGIES INC.
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L27/11578 ; H01L27/02 ; H01L27/11524 ; H01L27/11551 ; H01L27/1157 ; H01L27/11582

Abstract:
A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.
Public/Granted literature
- US20160293621A1 BRIDGE LINE STRUCTURE FOR BIT LINE CONNECTION IN A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE Public/Granted day:2016-10-06
Information query
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