Invention Grant
- Patent Title: Capacitance device in a stacked scheme and methods of forming the same
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Application No.: US14333307Application Date: 2014-07-16
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Publication No.: US09613994B2Publication Date: 2017-04-04
- Inventor: Yuichiro Yamashita
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/146
- IPC: H01L27/146

Abstract:
Embodiments of the present disclosure include devices and sensor packages and methods of forming the same. An embodiment is a device including a first semiconductor chip. The first semiconductor chip includes a first substrate, a first conductive pad over the first substrate. The device further includes a second semiconductor chip having a second surface bonded to a first surface of the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive pad over the second substrate. The second conductive pad and the first conductive pad form a first capacitor.
Public/Granted literature
- US20160020235A1 CAPACITANCE DEVICE IN A STACKED SCHEME AND METHODS OF FORMING THE SAME Public/Granted day:2016-01-21
Information query
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