Invention Grant
- Patent Title: Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
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Application No.: US15080231Application Date: 2016-03-24
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Publication No.: US09614102B2Publication Date: 2017-04-04
- Inventor: Chan-Long Shieh , Gang Yu , Fatt Foong
- Applicant: Chan-Long Shieh , Gang Yu , Fatt Foong
- Applicant Address: US CA Goleta
- Assignee: CBRITE INC.
- Current Assignee: CBRITE INC.
- Current Assignee Address: US CA Goleta
- Agency: Parsons & Goltry
- Agent Robert A. Parsons; Michael W. Goltry
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/12 ; H01L29/66 ; H01L21/70 ; H01L21/02
Abstract:
A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
Public/Granted literature
- US20160204278A1 SELF-ALIGNED METAL OXIDE TFT WITH REDUCED NUMBER OF MASKS AND WITH REDUCED POWER CONSUMPTION Public/Granted day:2016-07-14
Information query
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