An electronic device includes a semiconductor memory. The semiconductor memory includes first lines extending in a first direction; second lines extending in a second direction crossing the first direction; insulating patterns interposed between the first and second lines at first intersections of the first and second lines; and variable resistance patterns interposed between the first and the second lines at second intersections of the first and second lines. A central intersection is defined by respective central lines of the first and second lines and corresponds to a coordinate (0, 0). The first intersections are located on first to (n+1)th virtual lines, the (n+1)th virtual line having a polygonal shape in which vertexes correspond to coordinates (−(k−n), 0), (k−n, 0), (0, k−n) and (0, −(k−n)) where k is a natural number and n is an integer in a range of 0 to (k−1).