Invention Grant
- Patent Title: Methods and devices for stressing an integrated circuit
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Application No.: US13641984Application Date: 2011-04-19
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Publication No.: US09618567B2Publication Date: 2017-04-11
- Inventor: Florian Moliere , Sebastien Morand , Alexandre Douin , Gerard Salvaterra , Christian Binois , Daniel Peyre
- Applicant: Florian Moliere , Sebastien Morand , Alexandre Douin , Gerard Salvaterra , Christian Binois , Daniel Peyre
- Applicant Address: FR Blagnac
- Assignee: EUROPEAN AERONAUTIC DEFENCE AND SPACE COMPANY EADS FRANCE
- Current Assignee: EUROPEAN AERONAUTIC DEFENCE AND SPACE COMPANY EADS FRANCE
- Current Assignee Address: FR Blagnac
- Agency: Young & Thompson
- Priority: FR1052978 20100420
- International Application: PCT/EP2011/056235 WO 20110419
- International Announcement: WO2011/131669 WO 20111027
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Disclosed is in particular a device (2) for stressing an integrated circuit (1) including an electronic chip (10) mounted in a housing (12), the device including a source (20) of thermal stress. The device (2) also includes a thermally conductive coupling member (22), designed to be thermally coupled to the source (20) of thermal stress during the stressing operation. The coupling member (22) includes an end (220) whose geometry is suitable for being introduced into an aperture with a predefined geometry, to be made in the housing (12) of the integrated circuit (1) so as to thermally couple a coupling face (222) of this end (220) with a face (102) of the electronic chip (10).
Public/Granted literature
- US20130193995A1 METHODS AND DEVICES FOR STRESSING AN INTEGRATED CIRCUIT Public/Granted day:2013-08-01
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