An improved two-wire hall-effect speed sensor circuit includes two separate voltage regulation circuits. The voltage regulator circuits, hall plates, signal processing circuits, and output stage are implemented on an application specific integrated circuit (ASIC). In addition to a supply terminal and a return terminal, the ASIC includes an intermediate terminal. Both voltage regulation circuits may be aided by capacitors, one between the supply terminal and the return terminal, the other between the intermediate terminal and the return terminal. The speed sensor circuit is suitable for use with non-twisted wires, enabling use of a common supply wire for multiple sensors, thus reducing the number of terminals required on the controller and on connectors.