Invention Grant
- Patent Title: Driver IC of a display panel waiting a predetermined time before supplying vertical synchronization signal (VSYNC) after sleep-out command is received
-
Application No.: US14097174Application Date: 2013-12-04
-
Publication No.: US09619007B2Publication Date: 2017-04-11
- Inventor: Toshio Mizuno , Miho Kobayashi , Junpei Sakurai
- Applicant: Synaptics Japan GK
- Applicant Address: JP Tokyo
- Assignee: SYNAPTICS JAPAN GK
- Current Assignee: SYNAPTICS JAPAN GK
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2012-268290 20121207
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G09G3/36

Abstract:
An integrated circuit device includes first and second integrated circuits and a power supply line. The first integrated circuit includes a first power supply circuit, a timing generation circuit generating a synchronization signal, and a first power supply control section. The second integrated circuit includes a second power supply circuit and a second power supply control section. The power supply line electrically connects the outputs of the first and second power supply circuit. The first and second power supply control sections are each configured to start the operations of the first and second power supply circuits, respectively, in response to a start of a supply of the synchronization signal after a sleep-out command is supplied thereto. The timing generation circuit starts supplying the synchronization signal after a predetermined waiting time elapses after the sleep-out command is supplied to the first integrated circuit.
Public/Granted literature
Information query