Invention Grant
- Patent Title: Input space reduction for verification test set generation
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Application No.: US13755639Application Date: 2013-01-31
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Publication No.: US09619598B2Publication Date: 2017-04-11
- Inventor: Clifton A. Lyons, Jr. , Sudhir D. Kadkade , Kunal P. Ganeshpure
- Applicant: Mentor Graphics Corporation
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Banner & Witcoff, Ltd.
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50 ; G06F11/263

Abstract:
Various implementations of the invention provide for the determination of a test set that satisfies a coverage model, where portions of the search space need not be searched in order to generate the test set. With various implementations of the invention, a search space defined by a set of inputs for an electronic design and a coverage model is identified. The search space is then fractured into subspaces. Subsequently, the subspaces are solved to determine if they include at least one input sequence that satisfies the coverage constraints defined in the coverage model. The subspaces found to include at least one input sequence that satisfies these coverage constraints, are then searched for unique input sequences in order to generate a test set. Subspaces found not to include at least one input sequence that satisfies the coverage constraints may be excluded from the overall search space.
Public/Granted literature
- US20140013290A1 Input Space Reduction for Verification Test Set Generation Public/Granted day:2014-01-09
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