Invention Grant
- Patent Title: System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects
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Application No.: US13949549Application Date: 2013-07-24
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Publication No.: US09619605B1Publication Date: 2017-04-11
- Inventor: Vikas Kohli , Amit Kumar Sharma
- Applicant: CADENCE DESIGN SYSTEMS, INC.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Rosenberg, Klein & Lee
- Main IPC: G06F15/04
- IPC: G06F15/04 ; G06F17/50

Abstract:
A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.
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