Invention Grant
- Patent Title: Scalable geometry processing within a checkerboard multi-GPU configuration
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Application No.: US13976843Application Date: 2011-11-18
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Publication No.: US09619855B2Publication Date: 2017-04-11
- Inventor: Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
- Applicant: Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Lynch Law Patent Group, P.C.
- International Application: PCT/US2011/061447 WO 20111118
- International Announcement: WO2013/074124 WO 20130523
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T1/20 ; G06T15/10

Abstract:
Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
Public/Granted literature
- US20140306949A1 SCALABLE GEOMETRY PROCESSING WITHIN A CHECKERBOARD MULTI-GPU CONFIGURATION Public/Granted day:2014-10-16
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |