Invention Grant
- Patent Title: Retention voltages for integrated circuits
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Application No.: US15081869Application Date: 2016-03-26
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Publication No.: US09620200B1Publication Date: 2017-04-11
- Inventor: Sanjay Mangal , Gus Yeung , Martin Jay Kinkade , Rahul Mathur , Bal S. Sandhu , George McNeil Lattimore
- Applicant: ARM Limited
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Pramudji Law Group PLLC
- Agent Ari Pramudji
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/419 ; G11C11/413 ; G11C11/412 ; H01L27/11

Abstract:
Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.
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