Invention Grant
- Patent Title: Interconnection architecture for multilayer circuits
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Application No.: US14759725Application Date: 2013-01-18
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Publication No.: US09620204B2Publication Date: 2017-04-11
- Inventor: Warren Robinett
- Applicant: Hewlett-Packard Development Company, L.P.
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Houston
- Agent Fabian VanCott
- International Application: PCT/US2013/022262 WO 20130118
- International Announcement: WO2014/113024 WO 20140724
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C5/06 ; G11C5/02 ; G11C8/12 ; G11C7/18 ; G11C8/10 ; G11C8/14

Abstract:
A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided.
Public/Granted literature
- US20150357034A1 INTERCONNECTION ARCHITECTURE FOR MULTILAYER CIRCUITS Public/Granted day:2015-12-10
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