Invention Grant
- Patent Title: Method for fabricating non-volatile memory with ONO stack
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Application No.: US15175008Application Date: 2016-06-06
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Publication No.: US09620368B2Publication Date: 2017-04-11
- Inventor: Chien-Lung Chu , Chun-Hung Chen , Ta-Chien Chiu
- Applicant: Powerchip Technology Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Technology Corporation
- Current Assignee: Powerchip Technology Corporation
- Current Assignee Address: TW Hsinchu
- Agent Winston Hsu; Scott Margo
- Priority: TW103135549A 20141014
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/28 ; H01L29/49 ; H01L29/66 ; H01L29/06 ; H01L21/762 ; H01L29/40 ; H01L21/3105 ; H01L27/088 ; H01L27/11521 ; H01L27/11531
Abstract:
A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.
Public/Granted literature
- US20160284551A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2016-09-29
Information query
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