Invention Grant
- Patent Title: Semiconductor arrangement
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Application No.: US15160206Application Date: 2016-05-20
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Publication No.: US09620422B2Publication Date: 2017-04-11
- Inventor: Jean-Pierre Colinge , Chung-Cheng Wu , Sang Hoo Dhong , Ta-Pen Guo
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L29/78 ; H01L27/088 ; H01L29/66 ; B82Y10/00 ; B82Y40/00 ; H01L29/775 ; H01L21/8234
Abstract:
A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.
Public/Granted literature
- US20160268168A1 SEMICONDUCTOR ARRANGEMENT Public/Granted day:2016-09-15
Information query
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