Invention Grant
- Patent Title: Semiconductor chip, semiconductor package and fabricating method thereof
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Application No.: US14621574Application Date: 2015-02-13
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Publication No.: US09620460B2Publication Date: 2017-04-11
- Inventor: Hyun-Pil Noh , Jeong-Woon Kim , Seok-Ha Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2014-0082469 20140702; KR10-2014-0161076 20141118
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/58 ; H01L23/528 ; H01L23/31

Abstract:
Provided are a semiconductor chip, a semiconductor package and a fabricating method thereof, which can reduce or prevent cracks from being generated or propagated due to an external pressure. The semiconductor chip includes a semiconductor substrate including a first region and a second region, a plurality of interlayer insulation layers formed on the semiconductor substrate, a first crack stopper formed in the plurality of interlayer insulation layers of the first region, an interconnector formed in the plurality of interlayer insulation layers of the second region, a pad wire formed on the plurality of interlayer insulation layers, electrically connected to the interconnector in the second region and extending to the first region, a bonding pad on the plurality of interlayer insulation layers of the first region, electrically connected to the pad wire, and a protection layer covering the pad wire and exposing the bonding pad. The first crack stopper is positioned at a lower level than the bonding pad and is formed to completely surround the bonding pad while not overlapping with the bonding pad and not being connected to the pad wire.
Public/Granted literature
- US20160005697A1 SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF Public/Granted day:2016-01-07
Information query
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