Invention Grant
- Patent Title: Nonvolatile semiconductor memory device having word line hookup region with dummy word lines
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Application No.: US14842972Application Date: 2015-09-02
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Publication No.: US09620519B2Publication Date: 2017-04-11
- Inventor: Yasuyuki Baba , Kazuichi Komenaka , Hirofumi Inoue
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/792
- IPC: H01L29/792 ; H01L21/336 ; H01L27/11582 ; H01L27/11573 ; H01L27/11575

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including a first selection gate, word lines and a second selection gate stacked above a semiconductor substrate, and a memory pillar disposed through the first selection gate, word lines and second selection gate, a hookup region disposed adjacent to the memory cell array region in a first direction, and a dummy region disposed outside the memory cell array region and the hookup region, the dummy region including dummy word lines, each provided at the same layer as the associated word line.
Public/Granted literature
- US20160260722A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2016-09-08
Information query
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