Invention Grant
- Patent Title: Structure and method for reducing substrate parasitics in semiconductor on insulator technology
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Application No.: US14827183Application Date: 2015-08-14
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Publication No.: US09620617B2Publication Date: 2017-04-11
- Inventor: Paul D. Hurwitz
- Applicant: Newport Fab, LLC
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Bever, Hoffman & Harms, LLP
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L29/06 ; H01L27/12 ; H01L29/66 ; H01L21/84 ; H01L29/78 ; H01L29/786

Abstract:
A structure having improved electrical signal isolation and linearity is disclosed. The structure includes a buried oxide (“BOX”) layer over a bulk semiconductor layer, a device layer over the buried oxide layer, a compensation implant region near an interface of the buried oxide layer and the bulk semiconductor layer, wherein the compensation implant region is configured to substantially eliminate a parasitic conduction layer near the buried oxide layer. The compensation implant region has a doping concentration of at least one order of magnitude higher than a doping concentration of the bulk semiconductor layer. The structure includes a deep trench extending through the device layer and the buried oxide layer, and a damaged implant region in the bulk semiconductor layer near the deep trench. The structure also includes at least one transistor in the device layer.
Public/Granted literature
- US20160071927A1 Structure and Method for Reducing Substrate Parasitics in Semiconductor On Insulator Technology Public/Granted day:2016-03-10
Information query
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