Invention Grant
- Patent Title: Semiconductor device and method of manufacturing the semiconductor device
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Application No.: US15030192Application Date: 2014-10-30
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Publication No.: US09620632B2Publication Date: 2017-04-11
- Inventor: Jun Okawara , Yusuke Yamashita , Satoru Machida
- Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Applicant Address: JP Toyota
- Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Current Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
- Current Assignee Address: JP Toyota
- Agency: Oliff PLC
- Priority: JP2013-230092 20131106
- International Application: PCT/IB2014/002271 WO 20141030
- International Announcement: WO2015/068008 WO 20150514
- Main IPC: H01L29/36
- IPC: H01L29/36 ; H01L29/06 ; H01L27/06 ; H01L29/739 ; H01L29/861 ; H01L29/872 ; H01L29/08 ; H01L29/10 ; H01L29/66 ; H01L29/417

Abstract:
A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed. The pillar region has an n-type impurity, is formed on a lateral side of the body region, and extends along a depth from a top surface of the semiconductor substrate to a lower end of the body region. The barrier region has an n-type impurity and is formed on a lower side of the body region and the pillar region. The barrier region is formed on the lower side of the pillar region. An n-type impurity concentration distribution in a depth direction in the pillar region and the barrier region has a maximum value in the pillar region. The n-type impurity concentration distribution has a folding point on a side deeper than the maximum value.
Public/Granted literature
- US20160240641A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE Public/Granted day:2016-08-18
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