Invention Grant
- Patent Title: Apparatus and method for power MOS transistor
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Application No.: US14727276Application Date: 2015-06-01
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Publication No.: US09620635B2Publication Date: 2017-04-11
- Inventor: Chun-Wai Ng , Hsueh-Liang Chou , Po-Chih Su , Ruey-Hsin Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/148
- IPC: H01L27/148 ; H01L29/66 ; H01L29/76 ; H01L27/088 ; H01L29/78 ; H01L29/423 ; H01L29/10 ; H01L29/06

Abstract:
An apparatus comprises a buried layer over a substrate, an epitaxial layer over the buried layer, a first trench extending through the epitaxial layer and partially through the buried layer, a second trench extending through the epitaxial layer and partially through the buried layer, a dielectric layer in a bottom portion of the first trench, a first gate region in an upper portion of the first trench, a second gate region in the second trench, wherein the second gate region is electrically coupled to the first gate region, a drain region in the epitaxial layer and a source region on an opposite side of the first trench from the drain region.
Public/Granted literature
- US20150295077A1 Apparatus and Method for Power MOS Transistor Public/Granted day:2015-10-15
Information query
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