Processing logic circuit has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.