Invention Grant
- Patent Title: Bumpless build-up layer package warpage reduction
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Application No.: US14465325Application Date: 2014-08-21
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Publication No.: US09627227B2Publication Date: 2017-04-18
- Inventor: Pramod Malatkar , Drew W. Delaney
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/16 ; H01L25/00 ; H01L25/10 ; H01L23/00 ; H01L21/683

Abstract:
The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.
Public/Granted literature
- US20140363929A1 BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION Public/Granted day:2014-12-11
Information query
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