Invention Grant
- Patent Title: Method for building vertical pillar interconnect
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Application No.: US13826987Application Date: 2013-03-14
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Publication No.: US09627254B2Publication Date: 2017-04-18
- Inventor: Guy F. Burgess , Anthony P. Curtis , Eugene A. Stout , Theodore G. Tessier , Lillian C. Thompson
- Applicant: FlipChip International, LLC
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/56 ; H01L23/00
Abstract:
An exemplary method includes forming a vertical pillar overlying or laterally displaced from a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer. The method may include applying a solder sphere and/or solder flux in different combinations on top surfaces of different first and second pillars.
Public/Granted literature
- US20130196499A1 METHOD FOR BUILDING VERTICAL PILLAR INTERCONNECT Public/Granted day:2013-08-01
Information query
IPC分类:
