A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.