- Patent Title: Semiconductor device having a multi-level interconnection structure
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Application No.: US14813781Application Date: 2015-07-30
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Publication No.: US09627315B2Publication Date: 2017-04-18
- Inventor: Takeshi Morita
- Applicant: ROHM CO., LTD.
- Applicant Address: JP Kyoto
- Assignee: ROHM CO., LTD.
- Current Assignee: ROHM CO., LTD.
- Current Assignee Address: JP Kyoto
- Agency: Rabin & Berdo, P.C.
- Priority: JP2013-118146 20130604
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/528 ; H01L23/522

Abstract:
A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view.
Public/Granted literature
- US20170033041A1 SEMICONDUCTOR DEVICE HAVING A MULTI-LEVEL INTERCONNECTION STRUCTURE Public/Granted day:2017-02-02
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