Invention Grant
- Patent Title: Aspect ratio trapping and lattice engineering for III/V semiconductors
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Application No.: US15098683Application Date: 2016-04-14
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Publication No.: US09627491B2Publication Date: 2017-04-18
- Inventor: Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/267
- IPC: H01L29/267 ; H01L21/02 ; H01L21/762 ; H01L21/18 ; H01L29/06 ; H01L29/32
Abstract:
A semiconductor structure including a III/V layer on a SiGe layer, edges of the SiGe layer are relaxed, the III/V layer is a semiconductor in a III/V semiconductor group, the SiGe layer is directly on an insulator layer, barrier layers on two adjacent sides of the SiGe layer and the III/V layer, and the barrier layer is directly on the insulator layer.
Public/Granted literature
- US20160225861A1 ASPECT RATIO TRAPPING AND LATTICE ENGINEERING FOR III/V SEMICONDUCTORS Public/Granted day:2016-08-04
Information query
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