A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and a source line precharge path. The memory cell array may have a plurality of memory strings. The peripheral circuit may perform a program operation for the memory cell array. The control logic may control the peripheral circuit a channel precharge operation of the program operation. The source line precharge path may precharge channels of the plurality of memory strings through a source line of the memory cell array. The peripheral circuit may control, according to program data, a potential level of a selected one of a plurality of bit lines coupled to the plurality of memory strings during the channel precharge operation.