Invention Grant
- Patent Title: Copper etching integration scheme
-
Application No.: US15153967Application Date: 2016-05-13
-
Publication No.: US09633949B2Publication Date: 2017-04-25
- Inventor: Chih-Wei Lu , Chung-Ju Lee , Hsiang-Huan Lee , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/538 ; H01L23/528 ; H01L23/532 ; H01L21/768 ; H01L29/06 ; H01L23/522

Abstract:
The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.
Public/Granted literature
- US20160254225A1 COPPER ETCHING INTEGRATION SCHEME Public/Granted day:2016-09-01
Information query
IPC分类: