Invention Grant
- Patent Title: First-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and processing method thereof
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Application No.: US14901483Application Date: 2014-01-08
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Publication No.: US09633985B2Publication Date: 2017-04-25
- Inventor: Chih-Chung Liang , Yaqin Wang , Chunyan Zhang , Yu-Bin Lin , Youhai Zhang
- Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd.
- Applicant Address: CN Jiangsu
- Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd
- Current Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd
- Current Assignee Address: CN Jiangsu
- Agency: Honigman Miller Schwartz and Cohn LLP
- Agent Matthew H. Szalach; Jonathan P. O'Brien
- Priority: CN201310340538 20130806
- International Application: PCT/CN2014/000020 WO 20140108
- International Announcement: WO2015/018174 WO 20150212
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/00 ; H01L25/065 ; H01L23/495 ; H01L21/48 ; H01L21/56 ; H01L23/31
Abstract:
A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).
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