Invention Grant
- Patent Title: Floating-point adder circuitry
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Application No.: US15181747Application Date: 2016-06-14
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Publication No.: US09639326B2Publication Date: 2017-05-02
- Inventor: Tomasz Czajkowski
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F7/485
- IPC: G06F7/485 ; G06F17/10 ; G06F7/499 ; G06F5/01

Abstract:
An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.
Public/Granted literature
- US20160291934A1 FLOATING-POINT ADDER CIRCUITRY Public/Granted day:2016-10-06
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