Invention Grant
- Patent Title: Multiplication circuit providing dynamic truncation
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Application No.: US14453172Application Date: 2014-08-06
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Publication No.: US09639328B2Publication Date: 2017-05-02
- Inventor: Srinivasan Narayanamoorthy , Nam Sung Kim
- Applicant: Wisconsin Alumni Research Foundation
- Applicant Address: US WI Madison
- Assignee: Wisconsin Alumni Research Foundation
- Current Assignee: Wisconsin Alumni Research Foundation
- Current Assignee Address: US WI Madison
- Agency: Boyle Fredrickson, S.C.
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F7/523 ; G06F1/32 ; G06F7/499

Abstract:
A fixed-point multiplier providing reduced energy usage dynamically truncates received operands according to the location of computationally important bits in the operands and provides the truncated operands to a reduced width multiplier offering reduced energy usage. Information about the location of the dynamic truncation is used to properly shift the result of the multiplier to provide an approximation of full multiplication of the operands.
Public/Granted literature
- US20160041813A1 Multiplication Circuit Providing Dynamic Truncation Public/Granted day:2016-02-11
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