- Patent Title: Algorithm for vectorization and memory coalescing during compiling
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Application No.: US13660986Application Date: 2012-10-25
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Publication No.: US09639336B2Publication Date: 2017-05-02
- Inventor: Vinod Grover , Manjunath Kudlur , Michael Murphy
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/45 ; G06F9/50

Abstract:
One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.
Public/Granted literature
- US20130117548A1 ALGORITHM FOR VECTORIZATION AND MEMORY COALESCING DURING COMPILING Public/Granted day:2013-05-09
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