• Patent Title: Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions
  • Application No.: US13522382
    Application Date: 2010-01-25
  • Publication No.: US09639451B2
    Publication Date: 2017-05-02
  • Inventor: Constantin TudorSorin Babeanu
  • Applicant: Constantin TudorSorin Babeanu
  • Applicant Address: US TX Austin
  • Assignee: NXP USA, INC.
  • Current Assignee: NXP USA, INC.
  • Current Assignee Address: US TX Austin
  • International Application: PCT/IB2010/050312 WO 20100125
  • International Announcement: WO2011/089478 WO 20110728
  • Main IPC: G06F9/30
  • IPC: G06F9/30 G06F11/36
Debugger system, method and computer program product for utilizing hardware breakpoints for debugging instructions
Abstract:
Debugger system, method and computer program product for debugging instructions. The method for debugging instructions may include: receiving, by a debugger module, a group of instructions that are stored in a non-volatile memory module and is scheduled to be executed by a processor of a device; determining whether the group of instructions includes a conditional branch instruction; defining, by the debugger module, a hardware breakpoint address as an address of the conditional branch instruction if the group of instructions includes the conditional branch instruction; defining, by the debugger module, the hardware breakpoint as an address of a last instruction of the group of instructions to be executed if the group of instructions does not comprise the conditional branch instruction; instructing a hardware breakpoint detector of the device to detect the hardware breakpoint address; instructing the processor to execute instructions of the group of instructions in a continuous mode until the hardware breakpoint detector detects the hardware breakpoint address; instructing the processor to execute at least one instruction of the group of instructions in a single step mode after the hardware breakpoint detector detects the hardware breakpoint address; and receiving, from the device, debug information that is indicative of an execution of instructions by the processor.
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