To provide a semiconductor device having large memory capacity and high reliability of data or a small-size semiconductor device having a small circuit area. A memory cell includes first and second data retention portions capable of storing multilevel data. A data voltage is written to the first data retention portion from a first wiring through a transistor and a second wiring, and a data voltage is written to the second data retention portion from the second wiring through a transistor and the first wiring. With the configuration, data voltages reduced by the threshold voltages of the transistors can be retained in the first and second data retention portions. The written data voltages where the threshold voltages of the transistors are canceled can be read by precharging and then discharging the first wiring.