A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.