Invention Grant
- Patent Title: Reduced load memory module using wire bonds and a plurality of rank signals
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Application No.: US14645811Application Date: 2015-03-12
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Publication No.: US09640236B2Publication Date: 2017-05-02
- Inventor: Zhuowen Sun , Yong Chen
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C8/06
- IPC: G11C8/06 ; G11C5/06 ; G11C8/12 ; G06F12/00 ; G11C5/04

Abstract:
An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.
Public/Granted literature
- US20160267954A1 REDUCED LOAD MEMORY MODULE Public/Granted day:2016-09-15
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