Invention Grant
- Patent Title: Semiconductor memory device
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Application No.: US14991104Application Date: 2016-01-08
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Publication No.: US09640269B2Publication Date: 2017-05-02
- Inventor: Yasushi Nakajima , Hideaki Yamamoto
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/22 ; G11C16/26 ; G11C16/16 ; G11C29/02

Abstract:
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including a memory block, the memory block including a memory cell, the memory cell including a semiconductor layer, a conductive layer, and a charge accumulation layer, the charge accumulation layer being disposed between the semiconductor layer and the conductive layer; and a control circuit that executes an access operation on the memory cell, the control circuit, triggered by the access operation, detecting a leak current of the conductive layer, and when the leak current is a certain value or more, executing a faulty memory block processing that registers as an access-prohibited region the memory block including the conductive layer.
Public/Granted literature
- US20170062061A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2017-03-02
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