Invention Grant
- Patent Title: Method for via plating with seed layer
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Application No.: US15138033Application Date: 2016-04-25
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Publication No.: US09640431B2Publication Date: 2017-05-02
- Inventor: Shin-Yi Yang , Ching-Fu Yeh , Tz-Jun Kuo , Hsiang-Huan Lee , Ming-Han Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/288 ; C25D7/12 ; C25D3/38

Abstract:
Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
Public/Granted literature
- US20160240434A1 Method for Via Plating with Seed Layer Public/Granted day:2016-08-18
Information query
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