Invention Grant
- Patent Title: Method of manufacturing a semiconductor device with wider sidewall spacer for a high voltage MISFET
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Application No.: US15089932Application Date: 2016-04-04
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Publication No.: US09640440B2Publication Date: 2017-05-02
- Inventor: Koji Maekawa , Tatsuyoshi Mihara
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Young & Thompson
- Priority: JP2012-223643 20121005
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L21/265 ; H01L21/266 ; H01L21/311

Abstract:
An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.
Public/Granted literature
- US20160218040A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Public/Granted day:2016-07-28
Information query
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