Invention Grant
- Patent Title: Wafer bonding structures and wafer processing methods
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Application No.: US14597569Application Date: 2015-01-15
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Publication No.: US09640451B2Publication Date: 2017-05-02
- Inventor: Chao Zheng , Wei Wang , Junde Ma
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicant Address: CN Shanghai
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Anova Law Group, PLLC
- Priority: CN201410308855 20140630
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L21/304 ; H01L21/20 ; H01L21/66 ; H01L21/02 ; H01L21/78 ; H01L21/3065
Abstract:
A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.
Public/Granted literature
- US20150380327A1 WAFER BONDING STRUCTURES AND WAFER PROCESSING METHODS Public/Granted day:2015-12-31
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