A semiconductor device includes an isolation region laterally defining an active region in a semiconductor substrate, a gate structure positioned above the active region, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. An etch stop layer is positioned above and covers a portion of the active region, an interlayer dielectric material is positioned above the active region and covers the etch stop layer, and a confined raised source/drain region is positioned on and in contact with an upper surface of the active region. The confined raised source/drain region extends laterally between and contacts a lower sidewall surface portion of the sidewall spacer and at least a portion of a sidewall surface of the etch stop layer, and a conductive contact element extends through the interlayer dielectric material and directly contacts an upper surface of the confined raised source/drain region.