Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US15190677Application Date: 2016-06-23
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Publication No.: US09640642B2Publication Date: 2017-05-02
- Inventor: Shinya Sasagawa , Hitoshi Nakayama , Masashi Tsubuku , Daigo Shimada
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Robinson Intellectual Propery Law Office
- Agent Eric J. Robinson
- Priority: JP2010-161374 20100716
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/12 ; H01L29/66 ; H01L29/49 ; H01L29/45 ; H01L29/786 ; H01L27/088

Abstract:
When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.
Public/Granted literature
- US20160300933A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-10-13
Information query
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